RegViz: Visualize RCC_APB2SMENR Bitfield

STMicroelectronics /STM32GBK1CBT6 /RCC /RCC_APB2SMENR

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Interpret as RCC_APB2SMENR

TIM16SMEN=B_0x0, SYSCFGSMEN=B_0x0, TIM20SMEN=B_0x0, TIM15SMEN=B_0x0, SPI1SMEN=B_0x0, TIM8SMEN=B_0x0, TIM1SMEN=B_0x0, TIM17SMEN=B_0x0, SPI4SMEN=B_0x0, USART1SMEN=B_0x0, SAI1SMEN=B_0x0, HRTIM1SMEN=B_0x0

Description

APB2 peripheral clocks enable in Sleep and Stop modes register

Fields

SYSCFGSMEN	SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): SYSCFG + COMP + VREFBUF + OPAMP clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): SYSCFG + COMP + VREFBUF + OPAMP clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
TIM1SMEN	TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM1 timer clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM1P timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
SPI1SMEN	SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): SPI1 clocks disabled by the clock gating during⁽¹⁾ Sleep and Stop modes 1 (B_0x1): SPI1 clocks enabled by the clock gating during⁽¹⁾ Sleep and Stop modes
TIM8SMEN	TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM8 timer clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM8 timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
USART1SMEN	USART1clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): USART1clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): USART1clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
SPI4SMEN	SPI4 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): SPI4 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): SPI4 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop mode
TIM15SMEN	TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM15 timer clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM15 timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop mode
TIM16SMEN	TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM16 timer clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM16 timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
TIM17SMEN	TIM17 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM17 timer clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM17 timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
TIM20SMEN	TIM20 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM20 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM20 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
SAI1SMEN	SAI1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): SAI1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): SAI1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
HRTIM1SMEN	HRTIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): HRTIM1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): HRTIM1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes

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