SW=B_0x0, MCOSEL=B_0x0, MCOPRE=B_0x0, SWS=B_0x0
Clock configuration register
| SW | System clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force HSI16 oscillator selection when exiting stop and standby modes or in case of failure of the HSE oscillator. 0 (B_0x0): Reserved, must be kept at reset value 1 (B_0x1): HSI16 selected as system clock 2 (B_0x2): HSE selected as system clock 3 (B_0x3): PLL selected as system clock |
| SWS | System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 0 (B_0x0): Reserved, must be kept at reset value 1 (B_0x1): HSI16 oscillator used as system clock 2 (B_0x2): HSE used as system clock 3 (B_0x3): PLL used as system clock |
| HPRE | AHB prescaler Set and cleared by software to control the division factor of the AHB clock. Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to Section 6.1.5: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. 0xxx: SYSCLK not divided 8 (B_0x8): SYSCLK divided by 2 9 (B_0x9): SYSCLK divided by 4 10 (B_0xA): SYSCLK divided by 8 11 (B_0xB): SYSCLK divided by 16 12 (B_0xC): SYSCLK divided by 64 13 (B_0xD): SYSCLK divided by 128 14 (B_0xE): SYSCLK divided by 256 15 (B_0xF): SYSCLK divided by 512 |
| PPRE1 | APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided 4 (B_0x4): HCLK divided by 2 5 (B_0x5): HCLK divided by 4 6 (B_0x6): HCLK divided by 8 7 (B_0x7): HCLK divided by 16 |
| PPRE2 | APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided 4 (B_0x4): HCLK divided by 2 5 (B_0x5): HCLK divided by 4 6 (B_0x6): HCLK divided by 8 7 (B_0x7): HCLK divided by 16 |
| MCOSEL | Microcontroller clock output Set and cleared by software. Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. 0 (B_0x0): MCO output disabled, no clock on MCO 1 (B_0x1): SYSCLK system clock selected 2 (B_0x2): Reserved, must be kept at reset value 3 (B_0x3): HSI16 clock selected 4 (B_0x4): HSE clock selected 5 (B_0x5): Main PLL clock selected 6 (B_0x6): LSI clock selected 7 (B_0x7): LSE clock selected 8 (B_0x8): Internal HSI48 clock selected |
| MCOPRE | Microcontroller clock output prescaler These bits are set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed 0 (B_0x0): MCO is divided by 1 1 (B_0x1): MCO is divided by 2 2 (B_0x2): MCO is divided by 4 3 (B_0x3): MCO is divided by 8 4 (B_0x4): MCO is divided by 16 |