Regviz

STMicroelectronics /STM32H743x /QUADSPI /PIR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PIR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32H7x5_CM7/QUADSPI/PIR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTERVAL

Description

QUADSPI polling interval register

Fields

INTERVAL

Polling interval Number of CLK cycles between to read during automatic polling phases. This field can be written only when BUSY = 0.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data