STMicroelectronics /STM32H743x /RCC /C1_APB2LPENR

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Interpret as C1_APB2LPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM1LPEN)TIM1LPEN 0 (TIM8LPEN)TIM8LPEN 0 (USART1LPEN)USART1LPEN 0 (USART6LPEN)USART6LPEN 0 (SPI1LPEN)SPI1LPEN 0 (SPI4LPEN)SPI4LPEN 0 (TIM15LPEN)TIM15LPEN 0 (TIM16LPEN)TIM16LPEN 0 (TIM17LPEN)TIM17LPEN 0 (SPI5LPEN)SPI5LPEN 0 (SAI1LPEN)SAI1LPEN 0 (SAI2LPEN)SAI2LPEN 0 (SAI3LPEN)SAI3LPEN 0 (DFSDM1LPEN)DFSDM1LPEN 0 (HRTIMLPEN)HRTIMLPEN

Description

RCC APB2 Sleep Clock Register

Fields

TIM1LPEN

TIM1 peripheral clock enable during CSleep mode

TIM8LPEN

TIM8 peripheral clock enable during CSleep mode

USART1LPEN

USART1 Peripheral Clocks Enable During CSleep Mode

USART6LPEN

USART6 Peripheral Clocks Enable During CSleep Mode

SPI1LPEN

SPI1 Peripheral Clocks Enable During CSleep Mode

SPI4LPEN

SPI4 Peripheral Clocks Enable During CSleep Mode

TIM15LPEN

TIM15 peripheral clock enable during CSleep mode

TIM16LPEN

TIM16 peripheral clock enable during CSleep mode

TIM17LPEN

TIM17 peripheral clock enable during CSleep mode

SPI5LPEN

SPI5 Peripheral Clocks Enable During CSleep Mode

SAI1LPEN

SAI1 Peripheral Clocks Enable During CSleep Mode

SAI2LPEN

SAI2 Peripheral Clocks Enable During CSleep Mode

SAI3LPEN

SAI3 Peripheral Clocks Enable During CSleep Mode

DFSDM1LPEN

DFSDM1 Peripheral Clocks Enable During CSleep Mode

HRTIMLPEN

HRTIM peripheral clock enable during CSleep mode

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