Regviz

STMicroelectronics /STM32H750x /MDMA /MDMA_C3ISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MDMA_C3ISR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32H7x5_CM7/MDMA/MDMA_C3ISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEIF3)TEIF3 0 (CTCIF3)CTCIF3 0 (BRTIF3)BRTIF3 0 (BTIF3)BTIF3 0 (TCIF3)TCIF3 0 (CRQA3)CRQA3

Description

MDMA channel x interrupt/status register

Fields

TEIF3

Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
CTCIF3

Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
BRTIF3

Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
BTIF3

Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
TCIF3

channel x buffer transfer complete
CRQA3

channel x request active flag

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data