Regviz

STMicroelectronics /STM32H753x /CRS /ICR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ICR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32H7x5_CM7/CRS/ICR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYNCOKC)SYNCOKC 0 (SYNCWARNC)SYNCWARNC 0 (ERRC)ERRC 0 (ESYNCC)ESYNCC

Description

CRS interrupt flag clear register

Fields

SYNCOKC

SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.
SYNCWARNC

SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
ERRC

Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register.
ESYNCC

Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data