NAND Flash control registers
| PWAITEN | Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank: |
| PBKEN | NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus |
| PWID | Data bus width. These bits define the external memory device width. |
| ECCEN | ECC computation logic enable bit |
| TCLR | CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. |
| TAR | ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. |
| ECCPS | ECC page size. These bits define the page size for the extended ECC: |