This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
| IRS | Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. |
| ILS | Interrupt high-level status The flag is set by hardware and reset by software. |
| IFS | Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. |
| IREN | Interrupt rising edge detection enable bit |
| ILEN | Interrupt high-level detection enable bit |
| IFEN | Interrupt falling edge detection enable bit |
| FEMPT | FIFO empty. Read-only bit that provides the status of the FIFO |