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STMicroelectronics /STM32H753x /SDMMC1 /IDMABASE1R

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Interpret as IDMABASE1R

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IDMABASE1

Description

The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

Fields

IDMABASE1

Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0).

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data