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STMicroelectronics /STM32H7A3x /DMA2D /IFCR

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Interpret as IFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CTEIF)CTEIF 0 (CTCIF)CTCIF 0 (CTWIF)CTWIF 0 (CAECIF)CAECIF 0 (CCTCIF)CCTCIF 0 (CCEIF)CCEIF

Description

DMA2D interrupt flag clear register

Fields

CTEIF

Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register
CTCIF

Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
CTWIF

Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
CAECIF

Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
CCTCIF

Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
CCEIF

Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data