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STMicroelectronics /STM32H7A3x /DMA2D /LWR

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Interpret as LWR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LW

Description

DMA2D line watermark register

Fields

LW

Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data