STMicroelectronics /STM32H7A3x /EXTI /CPUEMR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CPUEMR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MR32)MR32 0 (MR33)MR33 0 (MR34)MR34 0 (MR35)MR35 0 (MR36)MR36 0 (MR37)MR37 0 (MR38)MR38 0 (MR39)MR39 0 (MR40)MR40 0 (MR41)MR41 0 (MR42)MR42 0 (MR43)MR43 0 (MR44)MR44 0 (MR46)MR46 0 (MR47)MR47 0 (MR48)MR48 0 (MR49)MR49 0 (MR50)MR50 0 (MR51)MR51 0 (MR52)MR52 0 (MR53)MR53 0 (MR54)MR54 0 (MR55)MR55 0 (MR56)MR56 0 (MR57)MR57 0 (MR58)MR58 0 (MR59)MR59 0 (MR60)MR60 0 (MR61)MR61 0 (MR62)MR62 0 (MR63)MR63

Description

EXTI event mask register

Fields

MR32

CPU Interrupt Mask on Direct Event input x+32

MR33

CPU Interrupt Mask on Direct Event input x+32

MR34

CPU Interrupt Mask on Direct Event input x+32

MR35

CPU Interrupt Mask on Direct Event input x+32

MR36

CPU Interrupt Mask on Direct Event input x+32

MR37

CPU Interrupt Mask on Direct Event input x+32

MR38

CPU Interrupt Mask on Direct Event input x+32

MR39

CPU Interrupt Mask on Direct Event input x+32

MR40

CPU Interrupt Mask on Direct Event input x+32

MR41

CPU Interrupt Mask on Direct Event input x+32

MR42

CPU Interrupt Mask on Direct Event input x+32

MR43

CPU Interrupt Mask on Direct Event input x+32

MR44

CPU Interrupt Mask on Direct Event input x+32

MR46

CPU Interrupt Mask on Direct Event input x+32

MR47

CPU Interrupt Mask on Direct Event input x+32

MR48

CPU Interrupt Mask on Direct Event input x+32

MR49

CPU Interrupt Mask on Direct Event input x+32

MR50

CPU Interrupt Mask on Direct Event input x+32

MR51

CPU Interrupt Mask on Direct Event input x+32

MR52

CPU Interrupt Mask on Direct Event input x+32

MR53

CPU Interrupt Mask on Direct Event input x+32

MR54

CPU Interrupt Mask on Direct Event input x+32

MR55

CPU Interrupt Mask on Direct Event input x+32

MR56

CPU Interrupt Mask on Direct Event input x+32

MR57

CPU Interrupt Mask on Direct Event input x+32

MR58

CPU Interrupt Mask on Direct Event input x+32

MR59

CPU Interrupt Mask on Direct Event input x+32

MR60

CPU Interrupt Mask on Direct Event input x+32

MR61

CPU Interrupt Mask on Direct Event input x+32

MR62

CPU Interrupt Mask on Direct Event input x+32

MR63

CPU Interrupt Mask on Direct Event input x+32

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