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STMicroelectronics /STM32H7A3x /RCC /C1_APB1HENR

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Interpret as C1_APB1HENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CRSEN)CRSEN 0 (SWPEN)SWPEN 0 (OPAMPEN)OPAMPEN 0 (MDIOSEN)MDIOSEN 0 (FDCANEN)FDCANEN

Description

RCC APB1 Clock Register

Fields

CRSEN

Clock Recovery System peripheral clock enable
SWPEN

SWPMI Peripheral Clocks Enable
OPAMPEN

OPAMP peripheral clock enable
MDIOSEN

MDIOS peripheral clock enable
FDCANEN

FDCAN Peripheral Clocks Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data