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STMicroelectronics /STM32H7A3x /RCC /CIER

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Interpret as CIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSIRDYIE)LSIRDYIE 0 (LSERDYIE)LSERDYIE 0 (HSIRDYIE)HSIRDYIE 0 (HSERDYIE)HSERDYIE 0 (CSIRDYIE)CSIRDYIE 0 (RC48RDYIE)RC48RDYIE 0 (PLL1RDYIE)PLL1RDYIE 0 (PLL2RDYIE)PLL2RDYIE 0 (PLL3RDYIE)PLL3RDYIE 0 (LSECSSIE)LSECSSIE

Description

RCC Clock Source Interrupt Enable Register

Fields

LSIRDYIE

LSI ready Interrupt Enable
LSERDYIE

LSE ready Interrupt Enable
HSIRDYIE

HSI ready Interrupt Enable
HSERDYIE

HSE ready Interrupt Enable
CSIRDYIE

CSI ready Interrupt Enable
RC48RDYIE

RC48 ready Interrupt Enable
PLL1RDYIE

PLL1 ready Interrupt Enable
PLL2RDYIE

PLL2 ready Interrupt Enable
PLL3RDYIE

PLL3 ready Interrupt Enable
LSECSSIE

LSE clock security system Interrupt Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data