STMicroelectronics /STM32H7B3x /Ethernet_MAC /DMACSR

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Interpret as DMACSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TI)TI 0 (TPS)TPS 0 (TBU)TBU 0 (RI)RI 0 (RBU)RBU 0 (RPS)RPS 0 (RWT)RWT 0 (ET)ET 0 (ER)ER 0 (FBE)FBE 0 (CDE)CDE 0 (AIS)AIS 0 (NIS)NIS 0TEB0REB

Description

Channel status register

Fields

TI

Transmit Interrupt

TPS

Transmit Process Stopped

TBU

Transmit Buffer Unavailable

RI

Receive Interrupt

RBU

Receive Buffer Unavailable

RPS

Receive Process Stopped

RWT

Receive Watchdog Timeout

ET

Early Transmit Interrupt

ER

Early Receive Interrupt

FBE

Fatal Bus Error

CDE

Context Descriptor Error

AIS

Abnormal Interrupt Summary

NIS

Normal Interrupt Summary

TEB

Tx DMA Error Bits

REB

Rx DMA Error Bits

Links

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