Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/STMicroelectronics/STM32H7x5_CM7/Ethernet_MAC/DMADSR#0x0
Debug status register
AHB Master Write Channel
DMA Channel Receive Process State
DMA Channel Transmit Process State
https://github.com/cmsis-svd/cmsis-svd-data