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STMicroelectronics /STM32H7B3x /Ethernet_MAC /MACLMIR

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Interpret as MACLMIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LSI0DRSYNCR 0LMPDRI

Description

Log message interval register

Fields

LSI

LSI
DRSYNCR

DRSYNCR
LMPDRI

LMPDRI

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data