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STMicroelectronics /STM32H7B3x /FMC /FMC_SDSR

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Interpret as FMC_SDSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RE)RE 0MODES1 0MODES2

Description

SDRAM Status register

Fields

RE

Refresh error flag An interrupt is generated if REIE = 1 and RE = 1
MODES1

Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1.
MODES2

Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data