Regviz

STMicroelectronics /STM32H7B3x /HRTIM_Common /ODSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ODSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32H7x5_CM7/HRTIM_Common/ODSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TA1ODS)TA1ODS 0 (TA2ODS)TA2ODS 0 (TB1ODS)TB1ODS 0 (TB2ODS)TB2ODS 0 (TC1ODS)TC1ODS 0 (TC2ODS)TC2ODS 0 (TD1ODS)TD1ODS 0 (TD2ODS)TD2ODS 0 (TE1ODS)TE1ODS 0 (TE2ODS)TE2ODS

Description

Output Disable Status Register

Fields

TA1ODS

Timer A Output 1 disable status
TA2ODS

Timer A Output 2 disable status
TB1ODS

Timer B Output 1 disable status
TB2ODS

Timer B Output 2 disable status
TC1ODS

Timer C Output 1 disable status
TC2ODS

Timer C Output 2 disable status
TD1ODS

Timer D Output 1 disable status
TD2ODS

Timer D Output 2 disable status
TE1ODS

Timer E Output 1 disable status
TE2ODS

Timer E Output 2 disable status

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data