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STMicroelectronics /STM32H7B3x /HRTIM_TIMB /OUTBR

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Interpret as OUTBR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (POL1)POL1 0 (IDLEM1)IDLEM1 0 (IDLES1)IDLES1 0FAULT1 0 (CHP1)CHP1 0 (DIDL1)DIDL1 0 (DTEN)DTEN 0 (DLYPRTEN)DLYPRTEN 0DLYPRT 0 (POL2)POL2 0 (IDLEM2)IDLEM2 0 (IDLES2)IDLES2 0FAULT2 0 (CHP2)CHP2 0 (DIDL2)DIDL2

Description

Timerx Output Register

Fields

POL1

Output 1 polarity
IDLEM1

Output 1 Idle mode
IDLES1

Output 1 Idle State
FAULT1

Output 1 Fault state
CHP1

Output 1 Chopper enable
DIDL1

Output 1 Deadtime upon burst mode Idle entry
DTEN

Deadtime enable
DLYPRTEN

Delayed Protection Enable
DLYPRT

Delayed Protection
POL2

Output 2 polarity
IDLEM2

Output 2 Idle mode
IDLES2

Output 2 Idle State
FAULT2

Output 2 Fault state
CHP2

Output 2 Chopper enable
DIDL2

Output 2 Deadtime upon burst mode Idle entry

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data