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STMicroelectronics /STM32H7B3x /HRTIM_TIME /TIMEICR

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Interpret as TIMEICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMP1C)CMP1C 0 (CMP2C)CMP2C 0 (CMP3C)CMP3C 0 (CMP4C)CMP4C 0 (REPC)REPC 0 (UPDC)UPDC 0 (CPT1C)CPT1C 0 (CPT2C)CPT2C 0 (SET1xC)SET1xC 0 (RSTx1C)RSTx1C 0 (SET2xC)SET2xC 0 (RSTx2C)RSTx2C 0 (RSTC)RSTC 0 (DLYPRTC)DLYPRTC

Description

Timerx Interrupt Clear Register

Fields

CMP1C

Compare 1 Interrupt flag Clear
CMP2C

Compare 2 Interrupt flag Clear
CMP3C

Compare 3 Interrupt flag Clear
CMP4C

Compare 4 Interrupt flag Clear
REPC

Repetition Interrupt flag Clear
UPDC

Update Interrupt flag Clear
CPT1C

Capture1 Interrupt flag Clear
CPT2C

Capture2 Interrupt flag Clear
SET1xC

Output 1 Set flag Clear
RSTx1C

Output 1 Reset flag Clear
SET2xC

Output 2 Set flag Clear
RSTx2C

Output 2 Reset flag Clear
RSTC

Reset Interrupt flag Clear
DLYPRTC

Delayed Protection Flag Clear

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data