STMicroelectronics /STM32H7B3x /RCC /C1_APB1HLPENR

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Interpret as C1_APB1HLPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CRSLPEN)CRSLPEN 0 (SWPLPEN)SWPLPEN 0 (OPAMPLPEN)OPAMPLPEN 0 (MDIOSLPEN)MDIOSLPEN 0 (FDCANLPEN)FDCANLPEN

Description

RCC APB1 High Sleep Clock Register

Fields

CRSLPEN

Clock Recovery System peripheral clock enable during CSleep mode

SWPLPEN

SWPMI Peripheral Clocks Enable During CSleep Mode

OPAMPLPEN

OPAMP peripheral clock enable during CSleep mode

MDIOSLPEN

MDIOS peripheral clock enable during CSleep mode

FDCANLPEN

FDCAN Peripheral Clocks Enable During CSleep Mode

Links

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