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STMicroelectronics /STM32H7B3x /RTC /RTC_ALRMBSSR

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Interpret as RTC_ALRMBSSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SS0MASKSS

Description

This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection.

Fields

SS

Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.
MASKSS

Mask the most-significant bits starting at this bit … The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data