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STMicroelectronics /STM32H7B3x /SPI1 /CGFR

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Interpret as CGFR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (I2SMOD)I2SMOD 0I2SCFG 0I2SSTD 0 (PCMSYNC)PCMSYNC 0DATLEN 0 (CHLEN)CHLEN 0 (CKPOL)CKPOL 0 (FIXCH)FIXCH 0 (WSINV)WSINV 0 (DATFMT)DATFMT 0I2SDIV0 (ODD)ODD 0 (MCKOE)MCKOE

Description

configuration register

Fields

I2SMOD

I2S mode selection
I2SCFG

I2S configuration mode
I2SSTD

I2S standard selection
PCMSYNC

PCM frame synchronization
DATLEN

Data length to be transferred
CHLEN

Channel length (number of bits per audio channel)
CKPOL

Serial audio clock polarity
FIXCH

Word select inversion
WSINV

Fixed channel length in SLAVE
DATFMT

Data format
I2SDIV

I2S linear prescaler
ODD

Odd factor for the prescaler
MCKOE

Master clock output enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data