STMicroelectronics /STM32H7x5_CM4 /ADC3 /ISR

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Interpret as ISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADRDY)ADRDY 0 (EOSMP)EOSMP 0 (EOC)EOC 0 (EOS)EOS 0 (OVR)OVR 0 (JEOC)JEOC 0 (JEOS)JEOS 0 (AWD1)AWD1 0 (AWD2)AWD2 0 (AWD3)AWD3 0 (JQOVF)JQOVF

Description

ADC interrupt and status register

Fields

ADRDY

ADC ready flag

EOSMP

ADC group regular end of sampling flag

EOC

ADC group regular end of unitary conversion flag

EOS

ADC group regular end of sequence conversions flag

OVR

ADC group regular overrun flag

JEOC

ADC group injected end of unitary conversion flag

JEOS

ADC group injected end of sequence conversions flag

AWD1

ADC analog watchdog 1 flag

AWD2

ADC analog watchdog 2 flag

AWD3

ADC analog watchdog 3 flag

JQOVF

ADC group injected contexts queue overflow flag

Links

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