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STMicroelectronics /STM32H7x5_CM4 /BDMA /CCR3

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Interpret as CCR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN)EN 0 (TCIE)TCIE 0 (HTIE)HTIE 0 (TEIE)TEIE 0 (DIR)DIR 0 (CIRC)CIRC 0 (PINC)PINC 0 (MINC)MINC 0PSIZE 0MSIZE 0PL0 (MEM2MEM)MEM2MEM

Description

DMA channel x configuration register

Fields

EN

Channel enable This bit is set and cleared by software.
TCIE

Transfer complete interrupt enable This bit is set and cleared by software.
HTIE

Half transfer interrupt enable This bit is set and cleared by software.
TEIE

Transfer error interrupt enable This bit is set and cleared by software.
DIR

Data transfer direction This bit is set and cleared by software.
CIRC

Circular mode This bit is set and cleared by software.
PINC

Peripheral increment mode This bit is set and cleared by software.
MINC

Memory increment mode This bit is set and cleared by software.
PSIZE

Peripheral size These bits are set and cleared by software.
MSIZE

Memory size These bits are set and cleared by software.
PL

Channel priority level These bits are set and cleared by software.
MEM2MEM

Memory to memory mode This bit is set and cleared by software.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data