STMicroelectronics /STM32H7x5_CM4 /DELAY_Block_SDMMC1 /CFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SEL0UNIT0LNG0 (LNGF)LNGF

Description

DLYB configuration register

Fields

SEL

Select the phase for the Output clock

UNIT

Delay Defines the delay of a Unit delay cell

LNG

Delay line length value

LNGF

Length valid flag

Links

()