STMicroelectronics /STM32H7x5_CM4 /FDCAN1 /FDCAN_TTILS

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Interpret as FDCAN_TTILS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SBCL)SBCL 0 (SMCL)SMCL 0 (CSML)CSML 0 (SOGL)SOGL 0 (RTMIL)RTMIL 0 (TTMIL)TTMIL 0 (SWEL)SWEL 0 (GTWL)GTWL 0 (GTDL)GTDL 0 (GTEL)GTEL 0 (TXUL)TXUL 0 (TXOL)TXOL 0 (SE1L)SE1L 0 (SE2L)SE2L 0 (ELCL)ELCL 0 (IWTGL)IWTGL 0 (WTL)WTL 0 (AWL)AWL 0 (CERL)CERL

Description

FDCAN TT Interrupt Line Select Register

Fields

SBCL

Start of Basic Cycle Interrupt Line

SMCL

Start of Matrix Cycle Interrupt Line

CSML

Change of Synchronization Mode Interrupt Line

SOGL

Start of Gap Interrupt Line

RTMIL

Register Time Mark Interrupt Line

TTMIL

Trigger Time Mark Event Internal Interrupt Line

SWEL

Stop Watch Event Interrupt Line

GTWL

Global Time Wrap Interrupt Line

GTDL

Global Time Discontinuity Interrupt Line

GTEL

Global Time Error Interrupt Line

TXUL

Tx Count Underflow Interrupt Line

TXOL

Tx Count Overflow Interrupt Line

SE1L

Scheduling Error 1 Interrupt Line

SE2L

Scheduling Error 2 Interrupt Line

ELCL

Change Error Level Interrupt Line

IWTGL

Initialization Watch Trigger Interrupt Line

WTL

Watch Trigger Interrupt Line

AWL

Application Watchdog Interrupt Line

CERL

Configuration Error Interrupt Line

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