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STMicroelectronics /STM32H7x5_CM4 /GPIOA /AFRL

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Interpret as AFRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0AFSEL00AFSEL10AFSEL20AFSEL30AFSEL40AFSEL50AFSEL60AFSEL7

Description

GPIO alternate function low register

Fields

AFSEL0

[3:0]: Alternate function selection for port x pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection:
AFSEL1

[3:0]: Alternate function selection for port x pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection:
AFSEL2

[3:0]: Alternate function selection for port x pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection:
AFSEL3

[3:0]: Alternate function selection for port x pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection:
AFSEL4

[3:0]: Alternate function selection for port x pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection:
AFSEL5

[3:0]: Alternate function selection for port x pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection:
AFSEL6

[3:0]: Alternate function selection for port x pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection:
AFSEL7

[3:0]: Alternate function selection for port x pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection:

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data