Regviz

STMicroelectronics /STM32H7x5_CM4 /HSEM /HSEM_MISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HSEM_MISR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32H7x5_CM7/HSEM/HSEM_MISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ISEM0)ISEM0 0 (ISEM1)ISEM1 0 (ISEM2)ISEM2 0 (ISEM3)ISEM3 0 (ISEM4)ISEM4 0 (ISEM5)ISEM5 0 (ISEM6)ISEM6 0 (ISEM7)ISEM7 0 (ISEM8)ISEM8 0 (ISEM9)ISEM9 0 (ISEM10)ISEM10 0 (ISEM11)ISEM11 0 (ISEM12)ISEM12 0 (ISEM13)ISEM13 0 (ISEM14)ISEM14 0 (ISEM15)ISEM15 0 (ISEM16)ISEM16 0 (ISEM17)ISEM17 0 (ISEM18)ISEM18 0 (ISEM19)ISEM19 0 (ISEM20)ISEM20 0 (ISEM21)ISEM21 0 (ISEM22)ISEM22 0 (ISEM23)ISEM23 0 (ISEM24)ISEM24 0 (ISEM25)ISEM25 0 (ISEM26)ISEM26 0 (ISEM27)ISEM27 0 (ISEM28)ISEM28 0 (ISEM29)ISEM29 0 (ISEM30)ISEM30 0 (ISEM31)ISEM31

Description

HSEM Masked interrupt status register

Fields

ISEM0

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM1

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM2

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM3

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM4

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM5

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM6

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM7

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM8

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM9

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM10

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM11

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM12

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM13

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM14

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM15

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM16

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM17

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM18

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM19

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM20

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM21

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM22

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM23

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM24

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM25

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM26

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM27

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM28

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM29

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM30

masked interrupt(N) semaphore n status bit after enable (mask)
ISEM31

masked interrupt(N) semaphore n status bit after enable (mask)

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data