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STMicroelectronics /STM32H7x5_CM4 /PWR /CSR1

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Interpret as CSR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PVDO)PVDO 0 (ACTVOSRDY)ACTVOSRDY 0ACTVOS 0 (AVDO)AVDO

Description

PWR control status register 1

Fields

PVDO

Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
ACTVOSRDY

Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3).
ACTVOS

VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU.
AVDO

Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data