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STMicroelectronics /STM32H7x5_CM4 /QUADSPI /PIR

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Interpret as PIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTERVAL

Description

QUADSPI polling interval register

Fields

INTERVAL

Polling interval Number of CLK cycles between to read during automatic polling phases. This field can be written only when BUSY = 0.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data