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STMicroelectronics /STM32H7x5_CM4 /RCC /APB1HRSTR

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Interpret as APB1HRSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CRSRST)CRSRST 0 (SWPRST)SWPRST 0 (OPAMPRST)OPAMPRST 0 (MDIOSRST)MDIOSRST 0 (FDCANRST)FDCANRST

Description

RCC APB1 Peripheral Reset Register

Fields

CRSRST

Clock Recovery System reset
SWPRST

SWPMI block reset
OPAMPRST

OPAMP block reset
MDIOSRST

MDIOS block reset
FDCANRST

FDCAN block reset

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data