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STMicroelectronics /STM32H7x5_CM4 /SCB /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NONBASETHRDENA)NONBASETHRDENA 0 (USERSETMPEND)USERSETMPEND 0 (UNALIGN__TRP)UNALIGN__TRP 0 (DIV_0_TRP)DIV_0_TRP 0 (BFHFNMIGN)BFHFNMIGN 0 (STKALIGN)STKALIGN 0 (DC)DC 0 (IC)IC 0 (BP)BP

Description

Configuration and control register

Fields

NONBASETHRDENA

Configures how the processor enters Thread mode
USERSETMPEND

USERSETMPEND
UNALIGN__TRP

UNALIGN_ TRP
DIV_0_TRP

DIV_0_TRP
BFHFNMIGN

BFHFNMIGN
STKALIGN

STKALIGN
DC

DC
IC

IC
BP

BP

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data