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STMicroelectronics /STM32H7x7_CM4 /DMA2D /DMA2D_ISR

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Interpret as DMA2D_ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEIF)TEIF 0 (TCIF)TCIF 0 (TWIF)TWIF 0 (CAEIF)CAEIF 0 (CTCIF)CTCIF 0 (CEIF)CEIF

Description

DMA2D Interrupt Status Register

Fields

TEIF

Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading).
TCIF

Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only).
TWIF

Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred.
CAEIF

CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D.
CTCIF

CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete.
CEIF

Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data