Regviz

STMicroelectronics /STM32H7x7_CM4 /MDMA /MDMA_C0ISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MDMA_C0ISR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32H7x5_CM7/MDMA/MDMA_C0ISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEIF0)TEIF0 0 (CTCIF0)CTCIF0 0 (BRTIF0)BRTIF0 0 (BTIF0)BTIF0 0 (TCIF0)TCIF0 0 (CRQA0)CRQA0

Description

MDMA channel x interrupt/status register

Fields

TEIF0

Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
CTCIF0

Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
BRTIF0

Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
BTIF0

Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
TCIF0

channel x buffer transfer complete
CRQA0

channel x request active flag

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data