This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
| BREN | Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. |
| MONEN | VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. |
| BRRDY | Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. |
| VBATL | VBAT level monitoring versus low threshold |
| VBATH | VBAT level monitoring versus high threshold |
| TEMPL | Temperature level monitoring versus low threshold |
| TEMPH | Temperature level monitoring versus high threshold |