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STMicroelectronics /STM32H7x7_CM4 /RAMECC1 /M1SR

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Interpret as M1SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ECCSEIE)ECCSEIE 0 (ECCDEIE)ECCDEIE 0 (ECCDEBWIE)ECCDEBWIE 0 (ECCELEN)ECCELEN

Description

RAMECC monitor x status register

Fields

ECCSEIE

ECC single error interrupt enable
ECCDEIE

ECC double error interrupt enable
ECCDEBWIE

ECC double error on byte write (BW) interrupt enable
ECCELEN

ECC error latching enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data