STMicroelectronics /STM32H7x7_CM4 /RCC /C1_APB4LPENR

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Interpret as C1_APB4LPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSCFGLPEN)SYSCFGLPEN 0 (LPUART1LPEN)LPUART1LPEN 0 (SPI6LPEN)SPI6LPEN 0 (I2C4LPEN)I2C4LPEN 0 (LPTIM2LPEN)LPTIM2LPEN 0 (LPTIM3LPEN)LPTIM3LPEN 0 (LPTIM4LPEN)LPTIM4LPEN 0 (LPTIM5LPEN)LPTIM5LPEN 0 (COMP12LPEN)COMP12LPEN 0 (VREFLPEN)VREFLPEN 0 (RTCAPBLPEN)RTCAPBLPEN 0 (SAI4LPEN)SAI4LPEN

Description

RCC APB4 Sleep Clock Register

Fields

SYSCFGLPEN

SYSCFG peripheral clock enable during CSleep mode

LPUART1LPEN

LPUART1 Peripheral Clocks Enable During CSleep Mode

SPI6LPEN

SPI6 Peripheral Clocks Enable During CSleep Mode

I2C4LPEN

I2C4 Peripheral Clocks Enable During CSleep Mode

LPTIM2LPEN

LPTIM2 Peripheral Clocks Enable During CSleep Mode

LPTIM3LPEN

LPTIM3 Peripheral Clocks Enable During CSleep Mode

LPTIM4LPEN

LPTIM4 Peripheral Clocks Enable During CSleep Mode

LPTIM5LPEN

LPTIM5 Peripheral Clocks Enable During CSleep Mode

COMP12LPEN

COMP1/2 peripheral clock enable during CSleep mode

VREFLPEN

VREF peripheral clock enable during CSleep mode

RTCAPBLPEN

RTC APB Clock Enable During CSleep Mode

SAI4LPEN

SAI4 Peripheral Clocks Enable During CSleep Mode

Links

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