STMicroelectronics /STM32H7x7_CM7 /ADC1_2 /CFGR

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Interpret as CFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMNGT 0RES0EXTSEL0EXTEN 0 (OVRMOD)OVRMOD 0 (CONT)CONT 0 (AUTDLY)AUTDLY 0 (DISCEN)DISCEN 0DISCNUM 0 (JDISCEN)JDISCEN 0 (JQM)JQM 0 (AWD1SGL)AWD1SGL 0 (AWD1EN)AWD1EN 0 (JAWD1EN)JAWD1EN 0 (JAUTO)JAUTO 0AWDCH1CH0 (JQDIS)JQDIS

Description

ADC configuration register 1

Fields

DMNGT

ADC DMA transfer enable

RES

ADC data resolution

EXTSEL

ADC group regular external trigger source

EXTEN

ADC group regular external trigger polarity

OVRMOD

ADC group regular overrun configuration

CONT

ADC group regular continuous conversion mode

AUTDLY

ADC low power auto wait

DISCEN

ADC group regular sequencer discontinuous mode

DISCNUM

ADC group regular sequencer discontinuous number of ranks

JDISCEN

ADC group injected sequencer discontinuous mode

JQM

ADC group injected contexts queue mode

AWD1SGL

ADC analog watchdog 1 monitoring a single channel or all channels

AWD1EN

ADC analog watchdog 1 enable on scope ADC group regular

JAWD1EN

ADC analog watchdog 1 enable on scope ADC group injected

JAUTO

ADC group injected automatic trigger mode

AWDCH1CH

ADC analog watchdog 1 monitored channel selection

JQDIS

ADC group injected contexts queue disable

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