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STMicroelectronics /STM32H7x7_CM7 /OTG_HS_PWRCLK /OTG_HS_PCGCR

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Interpret as OTG_HS_PCGCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STPPCLK)STPPCLK 0 (GATEHCLK)GATEHCLK 0 (PHYSUSP)PHYSUSP

Description

Power and clock gating control register

Fields

STPPCLK

Stop PHY clock
GATEHCLK

Gate HCLK
PHYSUSP

PHY suspended

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data