This register allows controlling CPU1 power.
| PDDS_D1 | D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. |
| PDDS_D2 | D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. |
| PDDS_D3 | System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. |
| HOLD2F | CPU2 on hold wakeup flag |
| STOPF | STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. |
| SBF | System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit |
| SBF_D1 | D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. |
| SBF_D2 | D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. |
| CSSF | Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. |
| HOLD2 | Hold the CPU2 and allocated peripherals when exiting from Stop mode |
| RUN_D3 | Keep system D3 domain in Run mode regardless of the CPU sub-systems modes |