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STMicroelectronics /STM32H7x7_CM7 /PWR /PWR_D3CR

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Interpret as PWR_D3CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (VOSRDY)VOSRDY 0VOS

Description

This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software

Fields

VOSRDY

VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3).
VOS

Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data