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STMicroelectronics /STM32H7x7_CM7 /QUADSPI /QUADSPI_DCR

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Interpret as QUADSPI_DCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CKMODE)CKMODE 0CSHT0FSIZE

Description

QUADSPI device configuration register

Fields

CKMODE

indicates the level that clk takes between command
CSHT

Chip select high time CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory. … This field can be modified only when BUSY = 0.
FSIZE

Flash memory size This field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. This field can be modified only when BUSY = 0.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data