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STMicroelectronics /STM32H7x7_CM7 /RCC /APB3ENR

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Interpret as APB3ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LTDCEN)LTDCEN 0 (DSIEN)DSIEN 0 (WWDG1EN)WWDG1EN

Description

RCC APB3 Clock Register

Fields

LTDCEN

LTDC peripheral clock enable
DSIEN

DSI Peripheral Clocks Enable
WWDG1EN

WWDG1 Clock Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data