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STMicroelectronics /STM32H7x7_CM7 /RCC /GCR

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Interpret as GCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WW1RSC)WW1RSC 0 (WW2RSC)WW2RSC 0 (BOOT_C1)BOOT_C1 0 (BOOT_C2)BOOT_C2

Description

RCC Global Control Register

Fields

WW1RSC

WWDG1 reset scope control
WW2RSC

WWDG2 reset scope control
BOOT_C1

Allows CPU1 to boot
BOOT_C2

Allows CPU2 to boot

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data