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STMicroelectronics /STM32H7x7_CM7 /SDMMC1 /SDMMC_MASKR

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Interpret as SDMMC_MASKR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCRCFAILIE)CCRCFAILIE 0 (DCRCFAILIE)DCRCFAILIE 0 (CTIMEOUTIE)CTIMEOUTIE 0 (DTIMEOUTIE)DTIMEOUTIE 0 (TXUNDERRIE)TXUNDERRIE 0 (RXOVERRIE)RXOVERRIE 0 (CMDRENDIE)CMDRENDIE 0 (CMDSENTIE)CMDSENTIE 0 (DATAENDIE)DATAENDIE 0 (DHOLDIE)DHOLDIE 0 (DBCKENDIE)DBCKENDIE 0 (DABORTIE)DABORTIE 0 (TXFIFOHEIE)TXFIFOHEIE 0 (RXFIFOHFIE)RXFIFOHFIE 0 (RXFIFOFIE)RXFIFOFIE 0 (TXFIFOEIE)TXFIFOEIE 0 (BUSYD0ENDIE)BUSYD0ENDIE 0 (SDIOITIE)SDIOITIE 0 (ACKFAILIE)ACKFAILIE 0 (ACKTIMEOUTIE)ACKTIMEOUTIE 0 (VSWENDIE)VSWENDIE 0 (CKSTOPIE)CKSTOPIE 0 (IDMABTCIE)IDMABTCIE

Description

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Fields

CCRCFAILIE

Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure.
DCRCFAILIE

Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure.
CTIMEOUTIE

Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout.
DTIMEOUTIE

Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout.
TXUNDERRIE

Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.
RXOVERRIE

Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.
CMDRENDIE

Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response.
CMDSENTIE

Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command.
DATAENDIE

Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end.
DHOLDIE

Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state.
DBCKENDIE

Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end.
DABORTIE

Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted.
TXFIFOHEIE

Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.
RXFIFOHFIE

Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.
RXFIFOFIE

Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full.
TXFIFOEIE

Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty.
BUSYD0ENDIE

BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response.
SDIOITIE

SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt.
ACKFAILIE

Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail.
ACKTIMEOUTIE

Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout.
VSWENDIE

Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion.
CKSTOPIE

Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped.
IDMABTCIE

IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data