STMicroelectronics /STM32L0x3 /RCC /APB2ENR

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Interpret as APB2ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSCFGEN)SYSCFGEN 0 (TIM21EN)TIM21EN 0 (TIM22EN)TIM22EN 0 (MIFIEN)MIFIEN 0 (ADCEN)ADCEN 0 (SPI1EN)SPI1EN 0 (USART1EN)USART1EN 0 (DBGEN)DBGEN

Description

APB2 peripheral clock enable register

Fields

SYSCFGEN

System configuration controller clock enable bit

TIM21EN

TIM21 timer clock enable bit

TIM22EN

TIM22 timer clock enable bit

MIFIEN

MiFaRe Firewall clock enable bit

ADCEN

ADC clock enable bit

SPI1EN

SPI1 clock enable bit

USART1EN

USART1 clock enable bit

DBGEN

DBG clock enable bit

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