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STMicroelectronics /STM32L4R7 /GFXMMU /B2CR

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Interpret as B2CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PBO0PBBA

Description

Graphic MMU buffer 2 configuration register

Fields

PBO

Physical buffer offset
PBBA

Physical buffer base address

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data