STMicroelectronics /STM32L4R7 /SDMMC1 /CMD

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Interpret as CMD

31282724232019161512118743000000000000000000000000000000000000000000CMDINDEX0WAITRESP0 (WAITINT)WAITINT0 (WAITPEND)WAITPEND0 (CPSMEN)CPSMEN0 (SDIOSuspend)SDIOSuspend0 (ENCMDcompl)ENCMDcompl0 (nIEN)nIEN0 (CE_ATACMD)CE_ATACMD

Description

command register

Fields

CMDINDEX

Command index

WAITRESP

Wait for response bits

WAITINT

CPSM waits for interrupt request

WAITPEND

CPSM Waits for ends of data transfer (CmdPend internal signal)

CPSMEN

Command path state machine (CPSM) Enable bit

SDIOSuspend

SD I/O suspend command

ENCMDcompl

Enable CMD completion

nIEN

not Interrupt Enable

CE_ATACMD

CE-ATA command

Links

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